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An efficient parallel prefix matching architecture using Bloom filter for multi-bit trie IP Lookup algorithm in FPGA

K. SARAVANAN1,* , A. SENTHILKUMAR2

Affiliation

  1. Department of electronics and communication, The Christian Institute for Technical education, Tamilnadu, India
  2. Professor, Department of Electrical and Electronics Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, India

Abstract

The major design challenge in Internet routers is the IP lookup, which is essential for packet forwarding. The Longest Prefix Matching (LPM) is used to obtain the best match for the incoming packets, which increases the time consumption of IP lookup. Current high speed link rate requires faster IP lookup. Due to the continuous increase in internet users, the routing table has to incorporate more routing entries for effective packet forwarding which results in memory usage increase. Various hardware based IP lookup mechanism using either TCAM or SRAM are available in use. TCAM–based solutions supports faster IP lookup with the high hardware cost and high power consumption compared to SRAM-based devices. The SRAM-based solutions require more memory access for IP lookup. This paper proposes parallel prefix matching using bloom filter for multi-bit trie based IP lookup, implemented in FPGA. The proposed method achieves faster IP lookup with single memory access. Comparison of implementation results shows that the proposed algorithm achieves 13.04 % increase in throughput and 27 times lesser memory usage..

Keywords

Longest Prefix Matching (LPM), Multi-bit trie, SRAM based IP lookup, Packet Forwarding.

Citation

K. SARAVANAN, A. SENTHILKUMAR, An efficient parallel prefix matching architecture using Bloom filter for multi-bit trie IP Lookup algorithm in FPGA, Optoelectronics and Advanced Materials - Rapid Communications, 9, 5-6, May-June 2015, pp.803-807 (2015).

Submitted at: March 10, 2015

Accepted at: May 7, 2015